A simple planar inductor

In Integrated Circuit design and MMIC design, integrated planar inductors are used frequently. These inductors have typically lower quality factors. However, in a variety of applications planar inductors can be used effectively. The simplest planar inductor is a length of high characteristic impedance microstrip line. A brief paper published by Signal Processing Group Inc.,provides design equations for this type of structure. Interested readers can view the paper at SPG's website, http://www.signalpro.biz on the engineering pages web page.

MEMS design tools

Its interesting how the MEMS design development is paralleling the IC design methodology of yesteryear. The process appears to be very similar,only the parameters seem to change. We also see UC Berkeley developing methodology and CAD tools. MIT is also an early entrant into the CAD Tool fray. Commercially available tools from Coventor are available ( for a significant cost) but may be the best deal for the design engineer interested in end results rather than the process. It remains to be seen how this whole industry pans out. However, already there are large numbers of MEMS devices working in commercial systems so the MEMS approach is beginning to make sense. Contact SPG at http://www.signalpro.biz for our experince with MEMS related issues.

Impedance matching: An example

Impedance matching is a key task in RF design and and also in lower frequency design where power transfer is an issue. A number of techniques exist to do this. Some are built-in scripts for advanced CAD programs while other techniques are manual. One of the techniques used quite commonly is the L - Section impedance matching technique. It is of interest to examine this technique. A recent technical memorandum released by the techteam at Signal Processing Group Inc. describes in some detail the matching of an antenna impedance and a resonant circuit associated with the antenna. It shows the detailed development of the matching circuit and checks that can be made to evaluate it. A PSPICE simulation is also shown along with the .cir file and plots. Interested readers are directed to the SPG website at http://www.signalpro.biz > "Engineer's Corner" for details.

The quarter wave matching transformer

In many high frequency applications matching a transmission line of known impedance to a known resistive load is an operation that is done over and over again. A simple way to do this is to use a quarter wave transformer. This concept is explained more fully in a paper released by Signal Processing Group Inc. recently. Interested readers may access this at the "engineer's corner" in the SPG website located at http://www.signalpro.biz.

Series to parallel conversion of LCR circuits

In a number of applications, specially in impedance matching LCR circuits may undergo series and parallel conversions. These conversions leave the performance of the circuit unchanged. They simply change the configurations to provide for a more appropriate architecture for the operation ( whatever that may be). A simple paper released by Signal Processing Group Inc. describes a method to do this. Interested parties may go to the website at http://www.signalpro.biz and access the paper from the "Engineer's Corner".

IC design and reliability: Failure distributions and the FIT

The failure rate for ICs is defined by: (Number of devices failed/Total number of devices tested)(1/time). The units can be stated as failures per device hour. This is an important parameter and has to be considered as early as possible in the design of the device. A unit called a FIT can also be defined. In this case a FIT = one failure per 1 billion device hours of operation. A FIT can be used to evaluate devices and distributions. The simplest model of failure is given by the parameter called the mean time to failure or MTTF. MTTF = 1/KF. Here KF is simply the failure rate per unit time. This is used in the exponential model which is very popular. The exponential model is simply expressed as: Fail(t) = 1.0 - exp(-KFt). This model is easy to use and calculate and can be used to assess the design of the device based on a failure rate model. Data is usually available from foundries for the use of this model. Please visit our website at http://www.signalpro.biz for more ASIC and module design and manufacturing information. Please contact SPG for detailed information on more extended types of failure expressions and their use in the design of devices. i.e how these failure parameters mesh with design parameters that allow the design to be more robust in terms of MTTF or failure rate.

IC design for mini(TM) and macro(TM) ASICs

We have divided the ASIC types that we develop into two categories. These are the miniASIC and the macroASIC. This nomenclature applies to the functionality, size, complexity and cost of the device. A miniASIC is a device with very few elements on it. It is small in size ( remember size differentiation; 50 mils on a side is small, 100 mils on a side is medium and 250 mils+ on a side is large for analog, RF, wireless or mixed signal ASICs). Examples are: 2 power/high voltage MOSFETs, a closely matched high frequency differential stage, multiple bipolars or MOSFETs on a chip (used largely for bread-boarding and proof of concept sometimes. Although these can be valuable adjuncts to a board design in production as well.) A low logic gate device, more logic gates than a CD4000 series device perhaps, but less than a large digital design ( 5k gates+). Matched resistors, capacitors, inductors and interconnect on a chip. A macroASIC on the other hand lies at the other end of the spectrum. It is a larger device,(definition above), it is more complex and costs more. In our experience both types come in handy when developing systems. The miniASIC can be used as part of glue circuitry ( when the exact device you need is not available of the shelf and it has to be cheap). The macroASIC is the device of choice when you want to sweep many discrete components on to a piece of silicon ( or GaAS, SiGe, GAN, etc)to provide enhanced performance, reduction in cost, safety of R&D, increased reliability and manufacturability, testability, and so on. Signal Processing Group Inc., provides both types of devices. The only drawback is of course that you cannot just go out and buy something quickly off the shelf. Lead times for these ASICS is of the order of 2 to 10 weeks. However, if the planning takes this into account then mini and maro ASICs become a sound choice. Please visit our website at http://www.signalpro.biz for more info.