RF Power Amplifier Design: Maximum Available Gain ( MAG)

When designing RF power amplifiers with active devices, it is always good to ask what the device is capable of in terms of power gain when everything is matched. i.e If I matched everything what is the maximum gain / performance I could get out of the device. The answer to this question lies in determining the MAG or Maximum Available Gain of the device. Of course, this is a theoretical quantity because it is not possible to get this performance in practice. The MAG then,is the theoretical power gain of a device when its reverse transfer characteristic or admittance/impedance is set to be non existent. In addition, its input and output ports must be conjugate matched with the source and load impedance respectively.Contact Signal Processing Group Inc., for all your RF Power Amplifier questons or needs. Please review RF power amplifier fundamental concepts at http://www.signalpro.biz/rfpa.pdf

Balun tutorial article

Baluns are used quite extensively in electronic design specially in higher frequency or differential circuits. The term "Balun" is an abbreviation for Balanced - Unbalanced. The implication is that a balun converts an unbalanced signal to balanced signals. In some ways Balun operation is not intuitive. An article describing the basics of baluns is presented by Signal Processing Group Inc.'s technical team and can be accessed at http://www.signalpro.biz/free_report_form_balun.html

Frequency modulation tutorial and simulations

FM signals are everywhere in the RF/Wireless world. Their resistance to noise and clean reception within their range of operation is exploited by many systems. It is useful sometimes to take a look at the theory behind these signals, at least to the point that an intuitive understanding can become beneficial. A recent paper by Signal Processing Group Inc., has been published that provides a description of the mathematics behind FM signals. A set of simulation results are provided that back up the theory. The paper can be accessed at the SPG website, http://www.signalpro.biz under " free stuff...".

IC design: Five good reasons to use ASICs and custom devices

Here are a number of reasons why you would want to develop your own ASIC or custom module, analog, RF or mixed signal. (1) You have developed a product using standard off the shelf components. When you did this your suppliers and their salepersons were all over you. Then the salesperson you knew left, or some other event took place. You no longer have the support from your supplier or distributor. Your project is stalled. Or even worse you have your product in the market and your supplier decides to discontinue the product you are using. The product is selling well. At this point you must have your own ASIC or module if you are to be independent of your supplier and their vicissitudes. It may take time and money but if market and product can support it, you must consider your own custom devices. (2) You have developed your product using off the shelf components. It is selling well. If the market is there and your product addresses the market, be assured your product will be copied and released to your market. You then have a number of choices. (A) Sue 'em. (B) Enhance your product. (C) Protect your IP (D) Exit the market. Only (C) is a palatable choice. You can do this by (E) Patents and trademarks (F) Hide your IP using full custom ASICs and modules (G) Enclose your product in a strong coating of some substance that is difficult to penetrate. Of these options we advocate full custom devices, ASICs or modules. You own the IP here, not your suppliers; It is very expensive to reverse engineer an ASIC and with the proper IP protection techniques ( coatings and other processes) it can be very difficult for a copycat to steal the IP. In addition if a portion of the IP is in firmware then this is an additional layer of protection. (3) Your product has been developed to the point of a demo model and it works. The boards and boxes are large and ungainly. You now have to fit it all in a really small area or enclosure. Again this is a really good reason to make your own custom ASIC or module. (4) Your product has been developed to the point of a demo model. It works fine except that it dissipates a lot of power. Perhaps it is a mobile unit and the batteries are running down. Whatever the case, this again is a really good rationale to get your own custom device. Custom devices can be designed to dissipate very little power using good low power techniques. (5) You have developed a product using discrete off the shelf devices. There are a lot of components on the board. This is causing a size increase and a manufacturing headache. Again use of a custom device is strongly recommended. Not only will the size and power come down but the overall product will be more reliable and easy to manufacture. If you want to learn more or develop your custom devices, please contact Signal Processing Group Inc, at http://www.signalpro.biz for a no obligation discussion or quotation. SPG uses state of the art semiconductor, PCB and assembly techniques to provide highly cost effective devices that belong to you.

Small loop antenna design

PCB small loop antenna design is required when designing with RF transmitter and receiver chips available as standard parts from a number of semiconductor manufacturers. A web survey turned up a small number of interesting and instructive articles on this topic. Of these articles only a very few met our purpose. Among these latter we found the most useful to be the one presented by Microchip Technology, Chandler, Arizona. ( Jan Van Niekirk, AN831). We generated an EXCEL spreadsheet using this article as a template for designing these types of antennas. It must be mentioned that this spreadsheet ( as well as the information in the article was found to be a starting point for the design. Some tweaking is still required using measurements.)This spreadsheet is available for download by interested parties from the SPG website located at http://www.signalpro.biz under Free Stuff.

IC design:Square roots of complex numbers

Now and then we come up against expressions in the design of circuits and systems that involve the use of complex numbers under the radical sign. When this happens it turns out that the whole technique is quite complicated and may involve De Moivre's theorem and polar form of complex numbers. Other techniques can be even more involved. Best of luck to the modelers who may be using these techniques. We found them at least as interesting as Bessels functions!

Summaries of papers presented at the 2012 IEEE custom IC conference.

Looking at the issue of the IEEE Journal of Solid State Circuits, after the 2012 Custom IC conference, with a critical eye for analog and RF content, the following interesting articles were found. A 3W class-D amplifier with improved linearity was described that reduces external filtering required for EMI protection by controlling the slew rate of the driver amplifier and digital modulation to spread the PWM common mode signal to place a null at the victim channel. The 110 nm CMOS design achieves SNR of 95 dB at 85% efficiency. A second article describes a 2.3 mW 10-bit 170 MS/s ADC in 65 nm CMOS using a two-step binary-search assisted time-interleaved SAR architecture. The third article , presents a continuous-time sigma-delta ADC with a switched-capacitor return-to-zero DAC that helps to reduce sensitivity to clock jitter and improves linearity. The prototype ADC was designed in a 180 nm process. It achieves an SNDR of 82.3 dB for a 2 MHz bandwidth while consuming 16.5 mW and reduces clock jitter sensitivity by 28 dB. An interesting article describes comprehensive design considerations for interleaved ADCs and proposes a background timing mismatch calibration technique to reduce the image to 75 dB for input frequencies more than 500 MHz. Another article presents a 40 nm 2.1 GS/s 2x time-interleaved pipeline ADC tthat uses a digital MDAC equalization techniques using FIR filters. The 12-bit design achieves SNDR of 52 dB while consuming 240 mW. In terms of topics in RF design some interesting articles described various RF techniques such as: A digital PLL that uses a coarse/fine TDC. The fine TDC is implemented using stochastic techniques to achieve an overall TDC resolution of 4 ps. The concept is demonstrated in a 130 nm 1.99–2.5 GHz PLL with 213 fs rms integrated jitter. The next paper in this series describes dynamic latches, where the regenerative cross-coupled pair is removed for maximum speed, demonstrated in prototypes of divide-by-4 circuits in 32 nm CMOS operated between 14 GHz and 70 GHz. A switched-triple-shielded transformer technique to realize a wideband CMOS VCO that can tune from 57.5 GHz to 90.1 GHz was also presented. An interesting paper provided reviews of techniques for improved harmonic reject mixers using clock gating that allow better than 52 dB rejection for 3rd/5th/7th LO harmonics without any calibration. This should be of interest to front end designers. There were papers on wireline topics as well. A paper presented a reference-less CDR for SONET transceivers that uses an algorithmic frequency acquisition without using a training sequence. The concept was demonstrated on a 65 nm transceiver that achieves 400s acquisition time and a jitter tolerance of 0.5 UI for 10 mVppd( differential) input sensitivity. Another paper on the wireline topics describes a 20 mW 6b 1.6 GS/s ADC with embedded partial equalization using a 1-tap DFE for serial receivers. The prototype receiver is demonstrated at 1.6 GS/s over 46-inch FR4 link with 14 dB loss while achieving a 0.2 UI timing margin. The next paper presented a 10 Gb/s 2-tap reconfigurable pre-emphasis transmitter that consumes 10 mW in a 65 nm LP CMOS. Power management was not ignored and papers described advances in power management techniques especially for SoC applications. An interesting paper for an adaptive all-digital ripple mitigation technique for fully integrated capacitive DC-DC converters was presented. Coarse ripple control was achieved by varying the size of the bucket capacitance, and fine control by time modulation of the charge/discharge charge transfer capacitors. The 130 nm design presented achieved 3x ripple reduction, 70% efficiency, and 24.5 mW/mm maximum power density. A power management unit was presented with a reconfigurable switched-capacitor converter in 65 nm CMOS to reduce the energy cost with sleep-to-active and active-to-sleep transitions by 64%. This energy reduction comes at small area overhead (lower than 1%) and no penalty in active mode. Another paper in the power management category presented a 190 nm CMOS, 87% efficiency, 0.75 mm on-chip feed-forward single inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation with 0.5 V startup. Its interesting to see that high voltage technology, techniques and circuits were glaringly missing from the issue that was based on the proceedings of the 2012 Custom Integrated Circuits Conference. There was a preponderance of papers utilizing analog technology ( and RF). Digital type technology was described but not in a large number of papers.